This invention relates generally to memory systems and in particular to systems having and memory array and associated reference arrays. Even more particularly, this invention relates to a method of erasing dual bit flash memory cells and associated reference arrays and a method of maintaining the functionality of the reference arrays.
Flash memory is a type of electronic memory media that can be rewritten and that can hold its content without the consumption of power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased and written in fixed multi-bit blocks or sectors. Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in situ. Flash memory devices are less expensive and denser, meaning that flash memory devices can hold more data per unit area. This new category of EEPROMs has emerged as an important non-volatile memory that combines the advantages of erasable programmable read only memory (EPROM) density with EEPROM electrical erasability.
Conventional flash memory devices are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as having a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a layer of tunnel oxide) formed on the surface of the substrate or P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a wordline associated with a row of such cells to form sectors of such cell in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell formed between the source and drain regions conducts current between the source and drain in accordance with an electric field formed in the channel by a voltage applied to the stacked gate structure by a wordline attached to the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a column is connected to the same bitline. In addition, the stacked gate structure of each flash cell in a row is connected to the same wordline. Typically, the source terminal of each cell is connected to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading and erasing the cell.
The single bit stacked gate flash memory cell is programmed by applying a programming voltage to the control gate, connecting the source to ground and connecting the drain to a programming voltage. The resulting high electric field across the tunnel oxide results in a phenomenon called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During Fowler-Nordheim tunneling, electrons in the channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, the control gate is held at a negative potential, and the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region. The electrons are then extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. The cell is erased as the electrons are removed from the floating gate.
In conventional single bit flash memory devices, erase verification is performed to determine whether each cell in a block or set of cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells that fail the initial verification. Thereafter, the erased status of the cell is again verified and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced that allow the storage of two bits of information in a single memory cell. The conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices. The dual bit flash memory structures do not utilize a floating gate, such as the ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. Techniques that have been developed with conventional single bit flash memory devices do not work well for the new dual bit flash memory cells.
The dual bit flash memory cell uses what is known as a virtual ground architecture in which the source of one bit serves as the drain of adjacent bits. During read operations the junction nearest the bit being read is the ground terminal and the other side of the cell is the drain terminal. This is called reverse read. The drain is switched during programming and erase back to the nearest junction using Vdrain voltage instead of ground, which is used for read and verify operations.
Another problem that has emerged is the charge loss after cycling of the cell. The inventors have determined that the major challenge for dual bit operation comes from the combination of the charge loss and complimentary bit disturb under the two conditions: 1. CBD (complimentary bit disturb) at BOL (beginning of life); and 2. Charge loss post cycling at EOL (end of life or post bake). Test data indicates that the CBD is higher near the BOL and the distributions overlay the program Vt after cycling and bake (EOL). The overlap of the two distributions prevents normal read sensing schemes from working correctly for double operations. In other words, it cannot be determined where the data in a CB or NB is a one or a zero because as the distributions approach each other, it cannot be reliably determined if the data is a one or a zero. This is because the data read from the cell is compared to static references. Another problem is that the charge loss (post cycling) for a programmed cell and a CBD are not in a 1 to 1 relationship. The post cycled CBD cell loses only about 60% of the total Vt that its program cell loses. Therefore, after cycling and bake normal sensing method to read CBD and zeros cannot be used.
As a result of the poor CBD to zero window after cycling and bake, alternative methods of read were developed and explored. Of the many alternative methods of read, a method was developed called the xe2x80x9cAverage Dynamic Reference Methodxe2x80x9d and was determined to be the best method and solved many of the problems associated with dual bit operation. The average dynamic reference method extended the usable life of the dual bit memory cell to the designed life. The average dynamic reference method uses two reference cells xe2x80x9caveragedxe2x80x9d and reads each bit only once to determine the data for each cell. The reference cells are erased at the same time the array is erased so that reference cells are the same xe2x80x9cagexe2x80x9d as the array cells because they have endured the same number of cycles as the data cells in the sector array. However, when the cells in a sector and the associated reference arrays are erased, it is then impossible to accurately read the cells in the reference array because the cells in the reference array have also been erased.
Therefore, what is needed is a method of recycling the sector array and reference array so that the reference array is available to read the sector array immediately after the sector is erased and before any programming of the sector array is done.
According to the present invention, the foregoing and other objects and advantages are achieved by a dual bit flash memory device having a plurality of sector arrays and a reference array associated with each sector array and which contain a plurality of dual bit flash memory cells.
In accordance with a first aspect of the invention, the dual bit flash memory cells in the associated reference arrays are cycled with the dual bit flash memory cells in the sector array so that all the cells in the sector arrays and associated reference arrays are the same xe2x80x9cage.xe2x80x9d
In accordance with a second aspect of the invention, the dual bit flash memory cells in the associated reference arrays are immediately programmed after being erased so that the reference arrays are ready to function as accurate references.
The described invention thus provides a dual bit flash memory array that allows dual bit operation of the flash memory device by allowing the use of dual dynamic references that are cycled with the dual bit memory cells in the flash memory and provides dual dynamic reference arrays that are immediately ready for use as references after a sector is erased.